Posts

📣 📣 📣 Prof. Zhou gave invited talks “Efficient Programming on Heterogeneous Accelerators” at University of Delaware, College of Engineering, Computer & Information Sciences Seminar and UD Mobility. You can watch the talk on YouTube now.

📣 📣 📣 Thrilled to share that our work ‘‘CLARE: Deterministic Cycle-Level Accelerator on REconfigurable platforms in DNN-Enabled Real-Time Safety-Critical Systems’’ has been accepted by the 46th IEEE Real-Time Systems Symposium 2025 (RTSS 2025)!

📣 📣 📣 Thrilled to share that our work ‘‘AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration’’ has been accepted by the International Conference for High Performance Computing, Networking, Storage and Analysis 2025 (SC 2025)!

📣 📣 📣 Thrilled to share that our work ‘ART: Customizing Accelerators for DNN-Enabled Real-Time Safety-Critical Systems’ has been accepted by the 35th ACM Great Lakes Symposium on VLSI 2025 (GLSVLSI 2025)!

📣 📣 📣 Thrilled to share that our work ‘ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines’ has been accepted by the 33rd ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'25) and won the Best Paper Nominee!

📣 📣 📣 Thrilled and deeply honored to share that our work ‘Amortizing Embodied Carbon Across Generations’ has been accepted by the 15th IEEE International Green and Sustainable Computing Conference (IGSC'24) and won the award of Best Viewpoint Paper!

Welcome Sarah! Sarah will join the lab in August 2024. Sarah graduated with Bachelor of Science in Electrical Engineering from University of Florida.

Welcome Wei! Wei will join the lab in August 2024. Wei graduated with Bachelor of Engineering and Master of Engineering in Electronics Science and Engineering from Southern University of Science and Technology of China, Shenzhen, China.

Prof. Peipei Zhou gave an invited talk in IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2024, Knoxville, Tennessee, on 07/03/2024 about SCARIF framework and paper “SCARIF: Towards Carbon Modeling of Cloud Servers with Accelerators”.

Our FPGA 2024 submission, “SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff Design Space Exploration” is accepted as full paper in FPGA 2024! Congratulations to my Ph.D. students Jinming Zhuang, Zhuoping Yang, and Shixin Ji!