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Bandwidth Optimization Through On-Chip Memory Restructuring for HLS
High-level synthesis (HLS) is getting increasing attention from both academia and industry for high-quality and high-productivity …
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Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
With the recent advancement of multilayer convolutional neural networks (CNN), deep learning has achieved amazing success in many …
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Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication
Customized pipeline designs that minimize the pipeline initiation interval (II) maximize the throughput of FPGA accelerators designed …
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A Fully Pipelined and Dynamically Composable Architecture of CGRA
Future processor chips will not be limited by the transistor resources, but will be mainly constrained by energy efficiency. …
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